Mixed-Signal Semiconductor Design

Low-Jitter Phase Lock Loop

iSine has developed a low-jitter (less than 10ps) phase lock loop cell with 4-phase output from 14-500MHz. Function proven in 0.13µm technology.

Features

Outline

This PLL Cell is designed for the TSMC 0.13µm process technology, but can also be used at 0.18µm. All loop filter components and dividers are fully integrated within the cell. A divide-by-N circuit is available to permit clock multiplication from a reference clock. A VCO post processing macro is available to produce VCO-half-rate and VCO-quarter-rate true and complement outputs. In addition, a four-phase (differential quadrature) direct VCO output clock is available. The VCO operates nominally at 280MHz, but is capable of operation from 140 to 500MHz. The cell achieves the frequency-multiply operations through the divider network shown in the PLL Cell Block Diagram below. Additionally, the feedback divide value is user selectable at each integer value between 4 and 16. For each valid M-divider value, recommended settings for two control bits are tabulated.

Available PLL Documentation

Contact Jeff Remmers for information.

PLL Cell Block Diagram

0.13µm PLL Block Diagram