IR Camera Signal Processing ASIC
The group at this mil-aero company won a DARPA contract to miniaturize an IR camera that would interface with an Android phone for display. While the design team had experience with IR cameras in military applications, they had previously used FPGAs (Field Programmable Gate Arrays) for the processing engine. Due to the small size and low power requirements, an FPGA would not be a viable solution. An ASIC (Application-Specific Integrated Circuit) was deemed necessary to meet the power and size restrictions. However, the length of time for ASIC development posed a challenge, as it would cause a delay in establishing a system model for software development and system integration. Additionally, the historical flexibility of using an FPGA for reprogramming after system release was lost with an ASIC, which required precision from the start.
iSine engineers collaborated with the mil-aero company to define the requirements for the ASIC and its operation in the system, covering aspects such as packaging and power. Once the specifications were thoroughly understood, documented, and agreed upon, the design phase commenced. The first phase resulted in a brassboard model for the ASIC, creating a subsystem that programmed the signal processing algorithms into FPGAs integrated into an early system version. This setup served as the platform for software development, system integration, evaluation, and modification before committing to the final ASIC. An early step in ASIC development involved defining the pinout or pad placement, considering the system requirements for stacking the ASIC with flash memory and DDR memory on a small 1-square printed circuit board.
The engineering team at the iSine was assembled to provide both design and verification groups for the core functions in the ASIC. These teams worked closely together but separately to ensure thorough verification and validation of the ASIC’s functionality and performance. The VHDL (VHSIC Hardware Description Language) written for the chip followed engineering standards, creating a code base that could be easily reused in future developments within the company. Testability was incorporated in both the logic and embedded memories to provide high-quality manufacturing tests for the final ASIC. After release to IBM for fabrication, the ASIC’s wafers underwent testing, leading to successful wafer dicing and assembly. The ASIC achieved all the goals defined in the specifications and successfully met the DARPA program requirements. The ASIC methodology used provided a reusable VHDL code base that could benefit other groups within the mil-aero company’s design services.