A MEMS startup was behind schedule on design and layout for an analog-digital signal converter (ADC).


An iSine engineer worked on site full time and weekends using Cadence Virtuoso Module Generator software. Layout, DRC and LVS were completed on time.


The customer's chip was taped out on time. The engineer worked with the customer two more times to help with more tapeouts.

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iSine will work with you to finish your ASIC on schedule, under budget and right the first time.