IR Camera Signal Processing ASIC
Mil/Aero ASIC Assembly
The group at this MIL/AERO company won a DARPA contract to miniaturize an IR camera that would interface with an Android phone for display. While the design team had done many projects with IR cameras in military applications, they had previously used FPGAs (Field Programmable Gate Arrays) for the processing engine. Due to the small size and low power requirements, an FPGA would not be a viable solution. It would require an ASIC to meet the power and size restrictions.
The length of time for an ASIC development would cause a delay in getting a system model in place for software development and system integration. Also, since the historical model of using an FPGA provided an opportunity for the development team to ‘reprogram’ the FPGA, even after system was released. An ASIC does not lend itself to reprogramming – it had to be done right the first time.
iSine engineers met with this MIL/AERO company to define the requirements for the ASIC and the operation of the ASIC in the system (including packaging & power). Once the specification was fully understood, documented and agreed upon, design began.
The first phase resulted in a ‘brassboard’ model for the ASIC. A subsystem was assembled that programmed the signal processing algorithms into FPGA’s that were integrated into an early version of the ‘system’. This provided the platform for software development and system integration. It also provided an early system for evaluation and modification before committing to the final ASIC.
An early step in the ASIC development was defining the pinout or pad placement. This was determined by reviewing the system requirements of stacking the ASIC with a FLASH memory and DDR memory on the small (1” square) printed circuit board.
The iSine engineering team was assembled to provide both design and verification groups for the core functions in the ASIC. The two teams worked closely together (but separately) to ensure thorough verification and validation of the ASIC functionality and performance. The VHDL that was written for the chip followed engineering standards to provide a code base that could be easily reused in future developments at this MIL/AERO company. Testability was added to provide high quality manufacturing test for the final ASIC.
The ASIC was released to IBM for fabrication and wafers were provided to the company for wafer-level testing. Once manufacturing test was completed successfully, the wafers were shipped to the assembler for wafer dicing (cutting the wafer into individual die) and system assembly.
The ASIC met all of the goals as defined in the specifications and was successful in meeting the DARPA program requirements. The ASIC methodology that was used provided a reusable VHDL code base that could be used by other groups within this MIL/AERO company.